1. Field of the Invention
The invention relates to the field of semiconductor transistors and more particularly to a single transistor memory gain cell with long retention times.
2. Description of the Related Art
Semiconductor memory devices are widely employed in a wide variety of electronic devices such as consumer electronics, computer systems, etc. The semiconductor memory devices can provide storage capacity for operating software as well as data storage, such as for text files, audio/video files, etc. A popular and commonly employed type of memory is known as dynamic random access memory (DRAM). DRAM provides the advantage of relatively rapid ability to write and read data as well as a relatively simple circuit design which facilitates relatively high circuit density and corresponding large memory capacity.
FIG. 1 is a cross-sectional view of a typical prior art DRAM array where a plurality of individual DRAM cells are arrayed to define a memory circuit. These prior art DRAM cells are formed in a silicon-on-insulator (SOI) substrate where an active layer of silicon overlies an underlying buried oxide (BOX) layer. Alternating n-type and p-type regions are formed in the active layer with gate stacks formed to overlie the p-type regions so as to define an n-type metal oxide semiconductor (NMOS) transistor. The p-type regions are also isolated by the n-type regions disposed on either side and the underlying BOX layer to define floating bodies. As can be seen in FIG. 1, a generally planar structure is defined where the various components of the memory cells are aligned in a generally horizontal manner along the major plane of the SOI upon which the devices are made.
The usual utilization for the DRAM array is to interconnect the drain regions along a first direction with a bit/data line and the gates along a second direction via corresponding word lines such that an individual cell can be accessed by addressing the corresponding bit/data line and word line to read from, or write to, the individual cell where the bit/data line and word line intersect. The DRAM cell also typically includes a capacitor structure (not shown) to which the NMOS transistor is connected. The capacitor stores charge to define the logic state of the particular cell. The NMOS transistor acts as an access transistor such that by selecting a given access transistor, the charge storage state of the associated capacitor can be determined. An operational consideration of the DRAM cell is that, in silicon technologies, the thermally dependent carrier generation rate is such that the charge stored on the capacitor will leak over time so as to lose the stored logic state. Thus, the stored charge defining the stored data must be periodically refreshed. This is a well known and accepted characteristic of DRAM technology, however it would be advantageous if the speed, density, and writability advantages of the DRAM configuration could be maintained while eliminating the overhead and complication of performing the refresh operations.
There is also a continuing desire in the field for increased storage capacity of memory devices, such as DRAM memory, as well as a corresponding desire for increased speed of operation. This is frequently addressed by reducing the physical size of individual memory cells (scaling), thus allowing a greater circuit density and device count for a given area of semiconductor substrate in which the individual devices are formed. However, there are ever-present limitations to the degree to which further reduction in size and corresponding increase in the total count and density of individual devices may be practically realized with current semiconductor processing technologies.
One way of addressing these limitations is to employ innovative device architectures which may facilitate fabricating individual devices of reduced size. Examples of this can be described with the explanatory vehicle of a DRAM cell. A typical DRAM cell includes a single n-type metal oxide semiconductor (NMOS) transistor connected to a separate charge storage device, such as a capacitor. Thus, scaling to reduce the size of the DRAM cell involves scaling both the NMOS transistor and the capacitor charge storage device. Efforts have been made to further reduce the footprint, or amount of the planar surface of the substrate occupied by the DRAM cell, by incorporating vertical structures in the DRAM cell. For example, transistors and capacitor structures are known which extend vertically upwards from the substrate or downwards into the substrate, such as with a trench structure. Scaling however can lead to difficulties in operation of the devices as reduction in the size of the capacitor, as well as reduction in operating voltages reduces the available electrical signal output from the memory cells making reliable read/write operations to the memory cells more difficult. An additional difficulty is that with the reduced physical size and operating voltages attendant to scaling, so-called soft errors can more frequently arise when incident radiation, such as alpha particles, activates charge carriers in the cell structure which can lead to errors in the proper read/write of the intended logic state of an individual device.
A further difficulty is that trench capacitors formed in the trenches in the semiconductor substrate are subject to trench-to-trench charge leakage enabled by the parasitic transistor effect between adjacent trenches. As the fabrication dimensions are reduced, this leakage effect is enhanced which can drain the capacitor leading to a loss of stored data. Also, incident alpha particle radiation can generate whole/electron pairs in the semiconductor substrate which functions as one of the storage plates of the trench capacitors. This can also cause charge stored on the affected capacitor to dissipate, leading to the aforementioned soft errors. Stacked capacitors of a sufficient capacitance for reliable cell operation present a substantial vertical extent, thus also limiting further reductions in total cell size while maintaining reliable cell operation.
It will thus be appreciated that there is a continuing need for innovative memory cell architectures which can satisfy the continuing demand for reduced cell size and corresponding increase in device count and density while maintaining reliable device operation and feasible and economical fabrication. There is also a need for cell architectures of reduced dimensions which are resistant to errors, such as the soft errors induced by incident alpha particle radiation. There is also a desire for a writable memory technology that could eliminate the need for or substantially extend the intervals between refresh operations.